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OKI Semiconductor ML675001/Q5002/Q5003
32-bit ARM-Based General-Purpose Microcontroller
FEDL675001-01
Issue Date: Dec. 15, 2003
GENERAL DESCRIPTION
The ML675001, ML67Q5002, and ML67Q5003 microcontrollers (MCUs) are the members of an extensive and growing family of 32-bit ARM(R)-based standard products for general-purpose applications that require 32-bit CPU performance and low cost afforded by MCU integrated features. ML675001/67Q5002/67Q5003 provide 8KB unified cache memory, built-in 32Kbyte SRAM, built-in 4Kbyte boot ROM, and a host of other useful peripherals such as auto-reload timers, watchdog timer (WDT), pulse-width modulators (PWM), A-to-D converter, expanded UARTs, synchronous serial port, I2C serial interface, GPIOs, DMA controller, external memory controller, and boundary scan capability. In addition, the ML67Q5002 and ML67Q5003 offer 256 Kbytes and 512 Kbytes of built-in Flash memory respectively. The ML675001, ML67Q5002 and ML67Q5003 are pin-to-pin compatible with each other, and are pin-to-pin compatible with ML674001 Series for easy performance updates. Oki's ML675K Family MCUs are capable of executing both the 32-bit ARM instruction set for high-performance applications as well as the 16-bit Thumb(R) instruction set for high code-density, power-efficient applications. With an ARM7TDMI(R) core operating at 60 MHz maximum frequency, ARM ThumbTM capabilities, and robust feature sets, the ML675001 Series MCUs are suitable for an array of applications including high performance industrial controllers and instrumentation, telecom, PC peripherals, security/surveillance, test equipment, and a variety of consumer electronics devices. The ARM7TDMI(R) Advantage Oki's ML675K Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit proprietary MCU architectures to ARM's higher-performance, affordable, widely-accepted industry standard architecture and its industry-wide support infrastructure. The ARM industry infrastructure offers the system developers many advantages including software compatibility, many ready-to-use software applications, large choices among hardware and software development tools. These ARM-based advantages allow Oki's customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce their product time to market. In addition, migration of a design with an Oki standard MCU to an Oki custom solution is easily facilitated with its award-winning uPLATTM product development architecture.
FEATURES
* CPU 32-bit RISC CPU (ARM7TDMI) 32-bit instructions (ARM Instructions) and 16-bit instructions (Thumb Instructions) mixed General purpose registers : 31 x 32 bits Built-in Barrel shifter and multiplier (32 bit x 8 bit, Modified Booth's Algorithm) Little endian Built-in debug function Cache memory 8KB unified memory 4 way set-associative * Internal memory RAM 32KB (32-bit access) FLASH (16-bit access) ML675001 : ROM-less version ML67Q5002 : 256Kbytes ML67Q5003 : 512Kbytes
ARM, ARM7TDMI, Multi-ICE and AMBA are registered trademarks of ARM Ltd., UK. PLAT is Oki's trademark. The contents of this data sheet are subject to change for modification without notice. 1/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
* External memory controller ROM (FLASH): 16 Mbytes SRAM: 16 Mbytes DRAM: 64 Mbytes (SDRAM and EDO-DRAM support) External IO devices: 16 Mbytes x 2 banks, 4 Chip select pins Wait control input signal for each bank Independent programmable wait settings for each bank * Interrupt controller 28 sources: 23 internals and 5 externals (IRQ: 4, FIQ: 1) * DMA controller 2 channels: Dual address mode, cycle steal and burst tranfer mode * Timer 1 channel: 16-bit auto reload for operating system 6 channels: 16-bit auto reload for application 1 channel: 16 bit watchdog timer * Serial interface 1 channel: UART 1 channel: UART with 16-byte FIFO 1 channel: synchronous 1 channel: I2C (single master) * Parallel I/O Port 4 ports x 8 bits (bitwise input/output settings) 1 port x 10 bit (bitwise input/output settings) * PWM 2 channels x 16 bits * Analog-to-Digital Converter 4 channels x 10 bits * Power down mechanism Standby (all clock stop) and Halt (clock stop by each function block) Clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 base clock frequency) * JTAG interface Connectable to JTAG ICE * Power supply voltage Core section: 2.25 V to 2.75 V IO section: 3.0 V to 3.6 V PLL section: 2.25 V to 2.75 V Analog section: 3.0 V to 3.6 V * Operating frequency 1-60 MHz * Operating temperature (ambient temperature) -40C to +85C * Package 144-pin plastic LQFP (LQFP144-P-2020-0.50) 144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
2/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
BLOCK DIAGRAM
TDI TDO nTRST TMS TCK 5 Internal (MCP) FLASH ROM ML67Q5002 : 256KB ML67Q5003 : 512KB
PLAT-7D
ARM7TDMI Cache Mem. 8KB Cache Cont. AHB Bridge
AMBA AHB bus
TIC
External Memory controller
DRAMC
Internal RAM 32KB
PIOC[6:2] / XA[23:19] XA[18:0] XD[15:0] PIOC[7] / XWR XOE_N XWE_N XBWE_N[1:0] XROMCS_N XRAMCS_N XIOCS_N[3:0] XBS_N[1:0] PIOD[0] / XWAIT PIOD[1] / XCAS_N PIOD[2] / XRAS_N PIOD[3] / XSDCLK PIOD[4] / XSDCS_N PIOD[5] / XSDCKE PIOD[7:6] / XDQM[1:0]/XCAS_N[1:0]
APB Bridge
AMBA APB bus
IRC
Exp. IRC
Boot ROM 4KB APB Bridge
2 DMAC 2 2
PIOB[0] / DREQ[0] PIOB[2] / DREQ[1] PIOB[1] / DREQCLR[0] PIOB[3] / DREQCLR[1] PIOB[4] / TCOUT[0] PIOB[5] / TCOUT[1]
System TMR
UART
System Control
TMR 16bit x 6ch
PWM 16bit x 2ch
2
PIOC[1:0] / PWMOUT[1:0 PIOA[0] / SIN PIOA[1] / SOUT PIOA[2] / CTS PIOA[3] / DRS PIOA[4] / DCD PIOA[5] / DTS PIOA[6] / RTS PIOA[7] / RI PIOE[0] / SDO PIOE[1] / SDI PIOE[2] / SCLK PIOE[3] / SDA PIOE[4] / SCL AIN[3:0] VREF
RESET_N PIOB[6] / STXD PIOB[7] / SRXD OSC0 OSC1_N CKOE_N CKO PIOE[8:5] / EXINT[3:0] PIOE[9] / EFIQ_N VDD_CORE VDD_IO GND PLLVDD PLLGND AVDD AGND DRAME_N TEST TEST1 BSEL[1:0] FWR JSEL 5 PLL
WDT UART (16550) 8
SSIO
3
I2C
2
A/D GPIO
APB bus
5 42 PIOA[7:0] PIOB[7:0] PIOC[7:0] PIOD[7:0] PIOE[9:0]
3/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
PIN CONFIGURATION (TOP VIEW)
144-Pin Plastic LFBGA
13 N M L K J H G F E D C B A
12
11
10
9
8
7
6
5
XA[14]
4
XA[11]
3
XA[9]
2
XA[7]
1
XA[6]
PIOD[6]/ XIOCS_ XIOCS_ XRAMC XBWE_ PIOC[4]/ XDQM[1 XOE_N XA[16] N[3] N[1] S_N N[0] XA[21] ] PIOD[7]/ XIOCS_ XIOCS_ PIOC[7]/ PIOC[6]/ PIOC[2]/ XWE_N XA[17] XDQM[0 N[2] N[0] XWR XA[23] XA[19] ] PIOB[1]/ PIOB[2]/ PIOB[0]/ XROMC XBWE_ PIOC[5]/ PIOC[3]/ DREQC XA[18] DREQ[1] DREQ[0] S_N N[1] XA[22] XA[20] LR[0] PIOB[3]/ PIOB[5]/ DREQC TCOUT[ VDD_IO 1] LR[1] PIOC[0]/ PWMOU T[0] GND GND VDD_IO VDD_C VDD_IO ORE GND
XA[15]
XA[13]
XA[10]
XA[4]
XA[5]
XA[12]
VDD_IO
XA[8]
XA[2]
GND
GND
XA[3]
XA[0]
XD[13]
XA[1]
PIOB[4]/ PIOC[1]/ TCOUT[ PWMOU T[1] 0]
VDD_IO XD[15] VDD_C ORE
XD[11]
XD[14]
XBS_N[ XBS_N[ PIOD[0]/ VDD_C 0] 1] XWAIT ORE PIOD[2]/ PIOD[1]/ VDD_IO XRAS_N XCAS_N GND
XD[10]
NC
XD[12]
144pin LFBGA (TOP VIEW)
VDD_IO
XD[8]
CLKMD1
XD[9]
PIOD[4]/ PIOD[5]/ PIOD[3]/ XSDCS_ BSEL[1] XSDCK XSDCLK N E PIOE[7]/ PIOE[8]/ PIOE[5]/ BSEL[0] EXINT[2] EXINT[3] EXINT[0] PIOE[0]/ PIOE[6]/ PIOE[9]/ PIOE[2]/ PIOA[1]/ OSC1_N SCLK EXINT[1] EFIQ_N SDO SOUT TDI PIOE[1]/ SDI TDO CKO TMS CKOE_ N VDD_IO AVDD AIN[0] VREFN VDD_IO
GND
XD[7]
XD[6]
XD[5]
GND
XD[2]
CLKMD0
XD[4]
GND
VDD_IO
XD[3]
XD[1] RESET_ N
AIN[1]
AIN[3]
VDD_C PIOA[5]/ ORE DTR GND
FWR
XD[0]
nTRST
TCK
GND DRAME _N
PIOA[0]/ VREFP SIN TEST AIN[2]
AGND
PIOA[3]/ PIOA[7]/ PIOE[4]/ PIOB[7]/ DSR RI SCL SRXD
PLLVDD PLLGND
JSEL
OSC0
PIOA[2]/ PIOA[4]/ PIOA[6]/ PIOE[3]/ PIOB[6]/ TEST1 CTS DCD RTS SDA STXD
13
Notes:
12
11
10
9
8
7
6
5
4
3
2
1
NC pins are electrically unconnected in the package. NC pins can be connected to Vdd or GND.
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
144-Pin Plastic LQFP
XDQM[0]/XCAS_N[0] XDQM[1]/XCAS_N[1]
PWMOUT[1] PWMOUT[0] TCOUT[1] TCOUT[0] DREQCLR[1] DREQ[1]
SDO SDI SCLK EFIQ_N EXINT[3] EXINT[2] EXINT[1] EXINT[0]
XSDCKE XSDCS_N XSDCLK XRAS_N
108
107
106 105
104 103
102
101 100 99 98
(Secondary fun(Primary function) PLLVDD PLLGND CKO JSEL TMS TCK DRAME_N CKOE_N GND OSC0 OSC1_N VDD_IO TEST PIOA[0] PIOA[1] AVDD VREFP AIN[0] AIN[1] AIN[2] AIN[3] VREFN AGND GND PIOA[2] VDD_IO PIOA[3] PIOA[4] VDD_CORE PIOA[5] PIOA[6] PIOA[7] GND PIOE[3] PIOE[4] PIOB[6]
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
nTRST TDO TDI PIOE[2] PIOE[1] PIOE[0] PIOE[9] PIOE[8] PIOE[7] PIOE[6] PIOE[5] BSEL[1] BSEL[0] PIOD[5] PIOD[4] PIOD[3] PIOD[2] VDD_IO GND PIOD[1] PIOD[0] VDD_CORE XBS_N[1] XBS_N[0] GND PIOC[1] PIOC[0] PIOB[5] PIOB[4] PIOB[3] PIOB[2] VDD_IO PIOB[1] PIOB[0] PIOD[7] PIOD[6]
(Primary f
XCAS_N XWAIT
DREQCLR[0] DREQ[0]
(Seconda
(Primary functi (Secondary f
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
97 96
95
94 93
92 91
90
89 88
87 86
85
84 83
82 81
80
79 78
77 76
75
74 73
SIN SOUT
144pin LQFP (TOP VIEW)
CTS DSR DCD DTR RTS RI SDA SCL STXD
XIOCS_N[3] XIOCS_N[2] XIOCS_N[1] GND XIOCS_N[0] XRAMCS_N XROMCS_N XBWE_N[1] XBWE_N[0] XWE_N VDD_IO XOE_N PIOC[7] PIOC[6] VDD_CORE PIOC[5] PIOC[4] PIOC[3] VDD_IO PIOC[2] XA[18] GND XA[17] XA[16] XA[15] GND XA[14] XA[13] XA[12] XA[11] XA[10] VDD_IO XA[9] XA[8] XA[7] XA[6]
XWR XA[23] XA[22] XA[21] XA[20] XA[19]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(Secondary function)
Notes:
NC pins are electrically unconnected in the package. NC pins can be connected to Vdd or GND.
SRXD
(Primary function) TEST1 PIOB[7] FWR RESET_N VDD_IO XD[0] XD[1] XD[2] XD[3] XD[4] GND CLKMD0 XD[5] XD[6] GND XD[7] CLKMD1 VDD_IO XD[8] XD[9] XD[10] VDD_CORE NC XD[11] XD[12] VDD_IO XD[13] XD[14] XD[15] XA[0] XA[1] XA[2] XA[3] GND XA[4] XA[5]
5/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
LIST OF PINS
Pin
LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 BGA A1 B1 C3 C1 D3 C2 D1 E3 D2 E1 E4 E2 F1 F2 F4 F3 G2 G4 G3 G1 H3 H4 H2 J2 H1 J4 K2 J1 J3 K3 K1 L2 K4 L1 M2 M1 N1 N2 L3 N3
Primary Function Symbol
TEST1 PIOB[7] FWR RESET_N VDD_IO XD[0] XD[1] XD[2] XD[3] XD[4] GND CLKMD0 XD[5] XD[6] GND XD[7] CLKMD1 VDD_IO XD[8] XD[9] XD[10] VDD_CORE NC XD[11] XD[12] VDD_IO XD[13] XD[14] XD[15] XA[0] XA[1] XA[2] XA[3] GND XA[4] XA[5] XA[6] XA[7] XA[8] XA[9] I/O -- I/O I I VDD I/O I/O I/O I/O I/O GND I I/O I/O GND I/O I VDD I/O I/O I/O VDD -- I/O I/O VDD I/O I/O I/O O O O O GND O O O O O O
Secondary Function Symbol
-- SRXD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O -- I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIO receive signal
Description
Test mode input General port (with interrupt function) Test mode inout Reset input IO power supply External data bus External data bus External data bus External data bus External data bus GND Clock mode input External data bus External data bus GND External data bus Clock mode input I/O power supply External data bus External data bus External data bus CORE power supply NC External data bus External data bus I/O power supply External data bus External data bus External data bus External address output External address output External address output External address output GND External address output External address output External address output External address output External address output External address output
Description
6/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin
LQFP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 BGA L4 M3 N4 L5 M4 N5 K5 M5 N6 M6 K6 L6 M7 K7 L7 N7 L8 K8 M8 M9 N8 K9 M10 N9 L9 L10 N10 M11 K10 N11 M12 N12 N13 M13 L11 L13 K11 L12
Primary Function Symbol
VDD_IO XA[10] XA[11] XA[12] XA[13] XA[14] GND XA[15] XA[16] XA[17] GND XA[18] PIOC[2] VDD_IO PIOC[3] PIOC[4] PIOC[5] VDD_CORE PIOC[6] PIOC[7] XOE_N VDD_IO XWE_N XBWE_N[0] XBWE_N[1] XROMCS_N XRAMCS_N XIOCS_N[0] GND XIOCS_N[1] XIOCS_N[2] XIOCS_N[3] PIOD[6] PIOD[7] PIOB[0] PIOB[1] VDD_IO PIOB[2] I/O VDD O O O O O GND O O O GND O I/O VDD I/O I/O I/O VDD I/O I/O O VDD O O O O O O GND O O O I/O I/O I/O I/O VDD I/O
Secondary Function Symbol
-- -- -- -- -- -- -- -- -- -- -- -- XA[19] -- XA[20] XA[21] XA[22] -- XA[23] XWR -- -- -- -- -- -- -- -- -- -- -- -- XDQM[1]/XCAS _N[1] XDQM[0]/XCAS _N[0] DREQ[0] DREQCLR[0] -- DREQ[1] I/O -- -- -- -- -- -- -- -- -- -- -- -- O -- O O O -- O O -- -- -- -- -- -- -- -- -- -- -- -- O O I O -- I DMA request signal (CH1) INPUT/OUTPUT mask/CAS (MSB) INPUT/OUTPUT mask/CAS (LSB) DMA request signal (CH0) DREQ Clear Signal (CH0) External address output Transfer direction of external bus External address output External address output External address output External address output
Description
I/O power supply External address output External address output External address output External address output External address output GND External address output External address output External address output GND External address output General port (with interrupt function) I/O power supply General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) CORE power supply General port (with interrupt function) General port (with interrupt function) Output enable (excluding SDRAM) I/O power supply Write enable Byte write enable (LSB) Byte write enable (MSB) External ROM chip select External RAM chip select IO chip select 0 GND IO chip select 1 IO chip select 2 IO chip select 3 General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) I/O power supply General port (with interrupt function)
Description
7/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin
LQFP 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 BGA K13 J11 K12 J13 J10 J12 H13 H12 H10 H11 G12 G10 G11 G13 F11 F10 F12 E12 F13 E10 D12 E13 E11 D11 D13 C12 D10 C13 B12 B13 A13 A12 C11 A11 C10 B11 A10
Primary Function Symbol
PIOB[3] PIOB[4] PIOB[5] PIOC[0] PIOC[1] GND XBS_N[0] XBS_N[1] VDD_CORE PIOD[0] PIOD[1] GND VDD_IO PIOD[2] PIOD[3] PIOD[4] PIOD[5] BSEL[0] BSEL[1] PIOE[5] PIOE[6] PIOE[7] PIOE[8] PIOE[9] PIOE[0] PIOE[1] PIOE[2] TDI TDO nTRST PLLVDD PLLGND CKO JSEL TMS TCK DRAME_N I/O I/O I/O I/O I/O I/O GND O O VDD I/O I/O GND VDD I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I O I VDD GND O I I I I
Secondary Function Symbol
DREQCLR[1] TCOUT[0] TCOUT[1] PWMOUT[0] PWMOUT[1] -- -- -- -- XWAIT XCAS_N -- -- XRAS_N XSDCLK XSDCS_N XSDCKE -- -- EXINT[0] EXINT[1] EXINT[2] EXINT[3] EFIQ_N SCLK SDI SDO -- -- -- -- -- -- -- -- -- -- I/O O O O O O -- -- -- -- I O -- -- O O O O -- -- I I I I I I/O I O -- -- -- -- -- -- -- -- -- -- Interrupt input Interrupt input Interrupt input Interrupt input FIQ input SSIO clock SSIO Serial Data In SSIO Serial Data Out Row address strobe (SDRAM/EDO-DRAM) Clock for SDRAM Chip select for SDRAM Clock enable (SDRAM) Wait input signal for I/O Banks Column address strobe (SDRAM) (CH1)
Description
General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) GND External bus byte select (LSB) External bus byte select (MSB) CORE power supply General port (with interrupt function) General port (with interrupt function) GND I/O power supply General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) Select boot device Select boot device General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) JTAG Data Input JTAG data out JTAG reset Power supply for PLL GND for PLL Clock output JTAG select JTAG mode select JTAG clock DRAM enable
Description
DREQ Clear Signal DMAC Terminal Count (CH0) DMAC Terminal Count (CH1) PWM output (CH0) PWM output (CH1)
8/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin
LQFP 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 BGA C9 B10 A9 D9 B9 A8 B8 D8 C8 B7 D7 C7 A7 C6 D6 B6 B5 A6 D5 B4 A5 C5 C4 A4 B3 D4 A3 B2 A2
Primary Function Symbol
CKOE_N GND OSC0 OSC1_N VDD_IO TEST PIOA[0] PIOA[1] AVDD VREFP AIN[0] AIN[1] AIN[2] AIN[3] VREFN AGND GND PIOA[2] VDD_IO PIOA[3] PIOA[4] VDD_CORE PIOA[5] PIOA[6] PIOA[7] GND PIOE[3] PIOE[4] PIOB[6] I/O I GND I O VDD I I/O I/O VDD I I I I I GND GND GND I/O VDD I/O I/O VDD I/O I/O I/O GND I/O I/O I/O
Secondary Function Symbol
-- -- -- -- -- -- SIN SOUT -- -- -- -- -- -- -- -- -- CTS -- DSR DCD -- DTR RTS RI -- SDA SCL STXD I/O -- -- -- -- -- -- I O -- -- -- -- -- -- -- -- -- I -- I I -- O O I -- I/O O O I2C Data In/Out I2C Clock out SIO send data output UART Data Terminal Ready UART Request To Send UART Ring Indicator UART Set Ready UART Carrier Detect UART Clear To Send UART Serial Data In UART Serial Data Out
Description
Clock out enable GND Oscillation input pin Oscillation output pin IO power supply Test mode input General port (with interrupt function) General port (with interrupt function) A/D CONVERTER power supply A/D CONVERTER Reference voltage A/D CONVERTER analog input port A/D CONVERTER analog input port A/D CONVERTER analog input port A/D CONVERTER analog input port Reference GND for A/D CONVERTER GND for A/D CONVERTER GND General port (with interrupt function) IO power supply General port (with interrupt function) General port (with interrupt function) CORE power supply General port (with interrupt function) General port (with interrupt function) General port (with interrupt function) GND General port (with interrupt function) General port (with interrupt function) General port (with interrupt function)
Description
9/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
PIN DESCRIPTION
Primary/ Logic Secondary
Pin Name System
RESET_N BSEL[1:0]
I/O
Description
I I
Reset input Boot device select signal BSEL[1] 0 0 1 after reset. BSEL[0] 0 1 * Boot device Internal Flash (External ROM for ML675001) External ROM Boot mode
--
Negative Positive
--
The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) CLKMD[1:0] OSC0 I I Clock mode input. Normally connect to ground level. -- Positive
Crystal connection or external clock input. Connect a crystal (5MHz to 14 MHz), if used, to OSC0 and OSC1_N. It is also possible to input a direct clock (5MHz to 14MHz, 20MHz to 56MHz). -- --
OSC1_N
O
Crystal connection. When not using a crystal, leave this pin unconnected.
-- -- --
-- -- Negative
CKO CKOE_N
O I
Clock out Clock out enable
Debugging support.
TCK TMS nTRST TDI TDO I I I I O Debugging pin. Normally connect to ground level. Debugging pin. Normally drive at High level. Debugging pin. Normally connect to ground level. Debugging pin. Normally drive at High level. Debugging pin. Normally leave open. -- -- -- -- -- -- Positive Negative Positive Positive
General-purpose I/O ports
PIOA[7:0] PIOB[7:0] PIOC[7:0] PIOD[7:0] I/O I/O I/O I/O General-purpose port. Not available for use as port pins when secondary functions are in use. General-purpose port. Not available for use as port pins when secondary functions are in use. General-purpose port. Not available for use as port pins when secondary functions are in use. General-purpose port. Not available for use as port pins when secondary functions are in use. Note that enabling DRAM controller with DRAME_N inputs permanently configures PIOD[7:0] for their secondary functions, making them unavailable for use as port pins. PIOE[9:0] I/O General-purpose port. Not available for use as port pins when secondary functions are in use. Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive
10/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin Name External Bus
XA[23:19]
I/O
Description
Primary / Secondary
Logic
O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM. After a reset, these pins are configured for their primary function (PIOC[6:2]).
Secondary
Positive
XA[18:0] XD[15:0]
O I/O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM. Data bus to external RAM, external ROM, external I/O banks, and external DRAM.
-- --
Positive Positive
External bus control signals (ROM/SRAM/IO)
XROMCS_N XRAMCS_N XIOCS_N[0] XIOCS_N[1] XIOCS_N[2] XIOCS_N[3] XOE_N XWE_N XBS_N[1:0] XBWE_N[0] XBWE_N[1] XWR O O O O O O O O O O O O ROM bank chip select SRAM bank chip select IO chip select 0 IO chip select 1 IO chip select 2 IO chip select 3 Output enable/ Read enable Write enable Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB LSB Write enable MSB Write enable Data transfer direction for external bus, used when connecting to Motorola I/O devices. This represent the secondary function of pin PIOC[7]. L: read , H: write. XWAIT I Available for I/O bank 0/1. Secondary Positive External I/O bank 0/1/2/3 WAIT signal. This input permits access to devices slower than register settings. -- -- -- -- -- -- -- -- -- -- -- Secondary Negative Negative Negative Negative Negative Negative Negative Negative Negative Negative Negative --
External bus control signals (DRAM)
XRAS_N XCAS_N XSDCLK XSDCKE XSDCS_N XDQM[1]/XCAS_N[1] XDQM[0]/XCAS_N[0] O O O O O O O Row address strobe. Used for both EDO DRAM and SDRAM Column address strobe signal (SDRAM) SDRAM clock (same frequency as internal HCLK) Clock enable (SDRAM) Chip select (SDRAM) Connected to SDRAM: DQM (MSB) Connected to EDO DRAM: column address strobe signal (MSB) Connected to SDRAM: DQM (LSB) Connected to EDO DRAM: column address strobe signal (LSB) Secondary Secondary Secondary Secondary Secondary Secondary Secondary Negative Negative -- -- Negative Positive/ Negative Positive/ Negative
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin Name DMA control signals
DREQ[0] DREQCLR[0] TCOUT[0] DREQ[1] DREQCLR[1] TCOUT[1]
I/O
Description
Primary / Secondary
Logic
I O O I O O
Ch 0 DMA request signal, used when DMA controller configured for DREQ type Ch 0 DREQ signal clear request. The DMA device responds to this output by negating DREQ. Indicates to Ch 0 DMA device that last transfer has started. Ch 1 DMA request signal, used when DMA controller configured for DREQ type Ch 1 DREQ signal clear request. The DMA device responds to this output by negating DREQ. Indicates to Ch 1 DMA device that last transfer has started
Secondary Secondary Secondary Secondary Secondary Secondary
Positive Positive Positive Positive Positive Positive
UART
SIN SOUT CTS I O I SIO receive signal SIO transmit signal Clear To Send. Indicates that modem or data set is ready to transfer data. modem status register reflects this input. DSR I Data Set Ready. Indicates that modem or data set is ready to establish a communications link with UART. Bit 5 in modem status register reflects this input. DCD I Data Carrier Detect. Indicates that modem or data set has detected data carrier signal. 7 in modem status register reflects this input. Data Carrier Detect DTR O Data Terminal Ready. Indicates that UART is ready to establish a communications link with modem or data set. output. RTS O Request To Send. Indicates that UART is ready to transfer data to modem or data set. Bit 1 in modem control register controls this output. RI I Ring Indicator. Indicates that modem or data set has received Secondary Negative telephone ring indicator. Bit 6 in modem status register reflects this input. Bit 0 in modem control register controls this Secondary Negative Secondary Negative Bit Secondary Negative Secondary Negative Bit 4 in Secondary Secondary Secondary Positive Positive Negative
SIO
STXD SRXD O I SIO transmit signal SIO receive signal Secondary Secondary Positive Positive
12/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Pin Name I2C
SDA SCL
I/O
Description
Primary / Secondary
Logic
I/O O
I2C Data. This pin operates as NMOS Open drain. Connect pull-up resistor. I2C Clock. This pin operates as NMOS Open drain. Connect pull-up resistor.
Secondary Secondary
Positive --
Synchronous SIO
SCLK SDI SDO I/O I O Serial clock Serial receive data Serial transmit data Secondary Secondary Secondary -- Positive Positive
PWM signals
PWMOUT[0] PWMOUT[1] O O PWM output of CH0 PWM output of CH1 Secondary Secondary Positive Positive
Analog-to-digital converter
AIN[0] AIN[1] AIN[2] AIN[3] VREFP VREFN AVDD AGND I I I I I I Ch0 analog input Ch1 analog input Ch2 analog input Ch3 analog input Analog-to-digital converter convert reference voltage Analog-to-digital converter convert reference GND Analog-to-digital converter power supply Analog-to-digital converter ground -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Interrupt signals
EXINT[3:0] EFIQ_N I I External interrupt input signals External fast interrupt input signal. Interrupt controller connects this to CPU FIQ input. Secondary Secondary Positive / Negative Negative
MODE configuration
DRAME_N TEST TEST1 FWR JSEL I I I I I DRAM enable mode Test mode Test mode Test mode JTAG select signal. L: On-board debug, H: Boundary scan. -- -- -- -- -- Negative Positive Positive Positive --
Power supplies
VDD_CORE VDD_IO GND PLLVDD PLLGND Core power supply I/O power supply GND for core and I/O PLL power supply GND for PLL -- -- -- -- -- -- -- -- -- --
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
DESCRIPTION OF FUNCTIONS
CPU CPU core: Operating frequency: Byte ordering: Instructions: General register bank: Built-in barrel shifter: Multiplier: Built-in debug function: ARM7TDMI 1 MHz to 60 MHz Little endian ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed. 31 x 32 bits ALU and barrel shift operations can be executed by one instruction. 32 bits x 8 bits (Modified Booth's Algorithm) JTAG interface, break point register
Built-in Memory FLASH ROM: ML675001 : ROM-less version ML67Q5002 : 256Kbytes (128K x 16 bits) ML67Q5003 : 512Kbytes (256K x 16 bits) Access timing of this FLASH memory is configured by the ROM bank control register of the external memory controller. RAM: 32KB (8K x 32bits) Read/Write access(8/16/32bit):3 cycle (cache memory unused) 8K unified memory with 4way set-associative
Cache memory:
Interrupt Controller Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as interrupt input signals. The interrupt controller controls these interrupt signals going to ARM core. (1) Interrupt sources FIQ: 1 external source (external pin: EFIQ_N) IRQ: total of 27 sources. 23 internal sources, and 4 external sources (external pins: EXINT[3:0]) (2) Interrupt priority level Configurable, 8-level priority for each source (3) External interrupt pin input EXINT[3:0] can be set as Level or Edge sensing. Configurable High or Low when Level sensing. Configurable Rise or Falling edge triggering when Edge sensing. EFIQ_N is set as Falling edge triggering.
Timers 7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS. The timers of other 6 channels are used in application software. (1) System timer: 1 channel 16-bit auto reload timer: Used as system timer for OS. Interrupt request by timer overflow. (2) Application timer: 6 channels 16-bit auto reload timer. Interrupt request by compare match. One shot, interval Clock can be independently set for each channel
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
WDT Functions as an interval timer or a watch dog timer. (1) (2) (3) (4) 16-bit timer Watch dog timer or interval timer mode can be selected Interrupt or reset generation Maximum period: longer than 200 msec
PWM This LSI contains two channels of PWM (Pulse Width Modulation) function which can change the duty cycle of a waveform with a constant period. The PWM output resolution is 16 bits for each channel. Serial Interface This LSI contains four serial interface. (1) UART without FIFO : 1 channel This is the serial port which performs data transmission, taking a synchronization per character. Selection of various parameters, such as addition of data length, a stop bit, and a parity bit, is possible. - Asynchronous full duplex operation - Sampling Rate = Baud rate x 16sample - Character Length : 7, 8 bit - Stop Bit Length : 1, 2 bit - Parity : Even, Odd, none - Error Detection : Parity, Framing, Over run - Loop Back Function : ON/OFF, Parity, framing, Over run Compulsive addition - Baud Rate Generation : Exclusive baud rate generator built-in (8bit counter) Independent from a bus clock - Internal-Baud-Rate-Clock-Stop at the time of HALT Mode. (2) UART with 16bytes FIFO : 1channel Features 16bytes FIFO in both send and receive. Uses the industry standard 16550A ACE (Asynchronous Communication Element). - Asynchronous full duplex operation - Reporting function for all status - 16 Byte Transmission and reception FIFO - Transmission, reception, interrupt of line status Data set and Independent FIFO control. - Modem control signals : CTS, DCD, DSR, DTR, RI and RTS - Data length : 5, 6, 7, 8 bit - Stop bit length : 1, 1.5, 2 bit - parity : Even, Odd, none - Error Detection : Parity, Framing, Overrun - Baud Rate Generation : Exclusive baud rate generator built-in (3) Synchronous serial interface : 1channel It is a clock synchronous 8bit serial port - selectable 1/8, 1/16 or 1/32 of HCLK frequency. - Choose LSB First or MSB First. - Choose Master / Slave Mode - Transceiver Interruption, Transceiver buffer empty interrupt - Loopback Test Function (4) I2C : 1channel Based on the I2C BUS specifications. Operates as a single master device. - Communication mode : Master transmitter /master receiver - Transmission Speed : 100kbps (Standard mode) / 400kbps (Fast mode) - Addressing format : 7 bit / 10 bit - Data buffer : 1 Byte(1step) - Communication Voltage : 2.7V to 3.3V
15/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
GPIO
42-bits parallel port (four 8-bit ports and one 10-bit port).
(1) (2) (3) (4) (5)
PIOA[7:0] Combination port UART PIOB[7:0] Combination port DMAC, UART(uPLAT-7B), PIOC[7:0] Combination port PWM, XA[23:19], XWR PIOD[7:0] Combination port DRAM contorol signal etc. PIOE[9:0] Combination port SSIO, I2C, External interrupt signal Input/output selectable at bit level. Each bit can be used as an interrupt source. Interrupt mask and interrupt polarity can be set for all bits. The ports are configured as input, immediately after reset. Primary/secondary function of each port can be set independently.
AD Converter Successive approximation type AD converter. (1) (2) (3) (4) (5) 10 bits x 4 channels Sample hold function Scan mode and select mode are supported Interrupt is generated after completion of conversion. Conversion time: 5 s minimum.
DMAC Two channels of direct memory access controller which transfers data between memory and memory, between I/O and memory and between I/O and I/O. (1) Number of channels: 2 channels (2) Channel priority level: Fixed mode Channel priority level is always fixed (channel 0 > 1). Roundrobin Priority level of the channel requested for transfer is kept lowest. (3) Maximum number of transfers: 65,536 times (64K times) (4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits) (5) Bus request system: Cycle steal mode Bus request signal is asserted for each DMA transfer cycle. Burst mode Bus request signal is asserted until all transfers of transfer cycles are complete. (6) DMA transfer request: Software request By setting the software transfer request bit inside DMAC, the CPU starts DMA transfer. External request DMA transfer is started by external request allocated to each channel. (7) Interrupt request: Interrupt request is generated to CPU after the end of DMA transfers for the set number of transfer cycles or after occurrence of error. Interrupt request signal is output separately for each channel. Interrupt request signal output can be masked for each channel.
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
External memory controller Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO devices, and internal FLASH memory. (1) ROM (FLASH) access function : 1 bank Supports 16-bit devices Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM). In ML67Q5002/ML67Q5003, control internal FLASH access. Configurable access timing. (2) SRAM access function : 1 bank Supports 16-bit devices Supports asynchronous SRAM Configurable access timing. (3) DRAM access function : 1 bank Supports 16-bit device Supports EDO/SDRAM : Simultaneous connections to EDO-DRAM and SDRAM cannot be made. Configurable access timing. (4) External IO access function : 2 banks Supports 8-bit/16-bit access : Independent configuration for each bank Each bank has two chip selects : XIOCS_N[3:0] Supports external wait input : XWAIT Access Timing configurable for each bank independently Power Management HALT, STANDBY, clock gear, clock control functions are supported as power save functions. (1) HALT mode HALT object CPU, internal RAM, AHB bus control HALT mode setting: Set by the system control register. Exit HALT mode due to: Reset, interrupt (2) STANDBY mode Stops the clock of entire LSI. STANDBY mode setting: Specified by the system control register. Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N) (3) Clock gear This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency. HCLK: CPU, bus control, synchronous serial interface, I2C. CCLK: Timers, PWM, UART, AD converter, etc. (4) Clock control by each function unit AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C.
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
BUILT-IN FLASH ROM PROGRAMMING
The robust features of the flash permit simple and optimized programming as well as maintaining the flash-ROM. (1) Programming Method * Programming via JTAG interface * Programming using boot mode Boot mode of this LSI is used for downloading data to be written to the FLASH through the UART interface of the MCU from a host system. In boot mode, the program on the on-chip boot ROM downloads a flash writing application, that will handle the serial transfer and writing of internal flash, to internal RAM area of the MCU through the UART interface of the MCU. * Programming via user application running from external memory Internal flash can be programmed by executing a user flash programming application from external memory. (2) Single power source for Read/Program of FLASH: 3.0V to 3.6V (3) Programming units : 2 bytes (4) Selectable erasing size * Sector erase: 2Kbytes/sector * Block erase: 64Kbytes/block * Chip erase: All memory cell (5) Word program time: 30usec (6) Sector/block erase time: 25msec (7) Chip erase time: 100msec (8) Write protection * Block protect: top address 8Kwords can be protected * Chip protect: all words can be protected (9) Number of commands: 9 (10) Highly reliable read/program * Sector programming: 1000 times * Data hold period: 10 years
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
ABSOLUTE MAXIMUM RATINGS*1
Item Digital power supply voltage (core) Digital power supply voltage (I/O) PLL power supply voltage Input voltage Output voltage Analog power supply voltage Analog reference voltage Analog input voltage Input current Output current Output current * *
2 3
Symbol VDD_CORE VDD_IO VDD_PLL VI VO AVDD VREF VAI II IO PD TSTG
Conditions
Rating -0.3 to +3.6 -0.3 to +4.6 -0.3 to +3.6 -0.3 to VDD_IO+0.3
Unit
GND = AGND = 0 V PLLGND = 0 V Ta = 25C
-0.3 to VDD_IO+0.3 -0.3 to VDD_IO+0.3 -0.3 to VDD_IO+0.3 and -0.3 to AVDD +0.3 -0.3 to VREF -10 to +10 -20 to +20 -30 to +30
V
mA
Power losses (LFBGA) Power losses (LQFP) Storage temperature
Ta = 85C per package --
680 1000 -50 to +150
mW C
Note 1. These are maximum ratings not for general operation. Exceeding these maximum ratings could cause damage or lead to permanent deterioration of the device. 2. All output pins except XA[15:0] 3. XA[15:0]
OPERATING CONDITIONS
(GND = 0 V) Item Digital power supply voltage (core) Digital power supply voltage (I/O) PLL power supply voltage Analog power supply voltage Analog reference voltage Operating frequency * Ambient temperature Symbol VDD_CORE VDD_IO VDD_CORE VDD_IO VDD_PLL AVDD VREF fOP Ta VDD_PLL = VDD_CORE AVDD = VDD_IO VREF = AVDD = VDD_IO VDD_CORE = 2.25 to 2.75 VDD_IO = 3.0 to 3.6 -- 3.0 2.25 3.0 3.0 1 -40 3.3 2.5 3.3 3.3 -- 25 3.6 2.75 3.6 3.6 60 85 MHz C V Conditions Minimum 2.25 Typical 2.5 Maximum 2.75 Unit
Note Oscillator frequencies between 5 MHz and 14 MHz. Minimum of 2.56 MHz for external SDRAM. Minimum of 6.4 MHz for external EDO DRAM. Minimum of 2 MHz for analog-to-digital converter.
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FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD_CORE = 2.25 to 2.75V, VDD_IO = 3.0 to 3.6V, Ta = -40 to +85C) Item High level input voltage Low level input voltage Schmitt input buffer threshold voltage High level output voltage Low level output voltage Low level output voltage * Input leak current *
3 1
Symbol VIH VIL VT+ VT- VHYS VOH
Conditions
Minimum VDD_IOx0.8 -0.3
Typical -- -- 1.6 1.1 0.5 -- -- -- -- -- -- -73 -- -- 6 9 10 320 1 20 10 37 6 75 17
Maximum VDD_IO+0.3 VDD_IOx0.2 2.1 -- -- -- -- 0.2 0.45 0.45 50 -10 5 50 -- -- -- 650 2 150 40 55 10 120 25
Unit
--
-- 0.7 0.4
IOH = -100 A IOH = -4 mA IOL = 100 A IOL = 4 mA IOL = 6 mA VI = 0 V/VDD_IO VI = 0 V Pull-up resistance of 50 k VI = AVDD / 0 V VO = 0 V/VDD_IO -- -- -- Analog-to-digital converter operative *6 Analog-to-digital converter stopped Ta = 25C *
7
VDD-0.2 2.35 -- -- -- -50 -200 -5 -50 -- -- -- -- -- -- -- -- -- -- --
V
VOL IIH/IIL IIL II ILO CI CO CIO IREF
Low level output voltage *2
Input leak current *4 Input leak current * Output leak current Input pin capacitance Output pin capacitance I/O pin capacitance Analog reference power supply current Current consumption (STANDBY) Current consumption 8 (HALT) * Current consumption (RUN) *9
5
A
pF
A
IDDS_CORE IDDS_IO IDDH_CORE IDDH_IO IDD_CORE IDD_IO
fOP = 60 MHz CL = 30 pF
mA
Notes 1. All output pins except XA[15:0] 2. XA[15:0] 3. All input pins except RESET_N 4. 5. 6. 7. 8. 9. RESET_N pin, with 50 k pull-up resistance Analog input pins (AIN0 to AIN3) Analog-to-Digital Converter operation ratio is 20% VDD_IO or 0 V for input ports; no load for other pins DRAM controller blocks stopped by DRAME_N pin setting Cacheable setting and external ROM used
20/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Analog-to-Digital Converter Characteristics
(VDD_CORE = 2.50 V, VDD_IO = 3.3 V, Ta = 25C) Item Resolution Linearity error Differential linearity error Zero scale error Full scale error Conversion time Throughput Symbol n EL ED EZS EFS tCONV Conditions -- Analog input source impedance Ri 1k -- -- Minimum Typical Maximum -- -- -- -- -- 5 10 -- 3 3 3 3 -- -- 10 -- -- -- -- -- 200 s kHz LSB Unit bit
Notes: VDD_IO and AVDD should be supplied separately * Definition of Terms (1) Resolution: Minimum input analog value recognized. For 10-bit resolution, this is (VREF - Aground) / 1024. (2) Linearity error: Difference between the theoretical and actual conversion characteristics. (Note that it does not include quantization error.) The theoretical conversion characteristic divides the voltage range between VREF and AGND into 1024 equal steps. (3) Differential linearity error: Difference between the theoretical and actual input voltage change producing a 1-bit change in the digital output anywhere within the conversion range. This is an indicator of conversion characteristic smoothness. The theoretical value is (VREF - Aground) / 1024. (4) Zero scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from "0x000" to "0x001." (5) Full scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from "0x3FE" to "0x3FF."
21/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
22/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
REVISION HISTORY
Document No.
PEDL675001-01 FEDL675001-01
Date
Feb.17, 2003 Dec.15, 2003
Page Previous Current Edition Edition
- - - -
Description
Preliminary edition 1 Final edition 1
23/24
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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